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(parent: 0a71ca9) | patch
x86/Intel: IceLake D + Sapphire Rapids Xeons also support PPIN
authorJan Beulich <jbeulich@suse.com>
Thu, 27 Jan 2022 12:50:19 +0000 (13:50 +0100)
committerJan Beulich <jbeulich@suse.com>
Thu, 27 Jan 2022 12:50:19 +0000 (13:50 +0100)
commitdf6f5cd9e51e742b23dcee99907e97a435716061
tree7a6489d00146cadb907e2e3b97cd8a4da74db163tree | snapshot
parent0a71ca9ab4c2d9a44f972c517bafa332b1622c10commit | diff
x86/Intel: IceLake D + Sapphire Rapids Xeons also support PPIN

This is as per Linux commits a331f5fdd36d ("x86/mce: Add Xeon Sapphire
Rapids to list of CPUs that support PPIN") and [tip.git] e464121f2d40
("x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN"), just
in case a subsequent change making use of the respective new CPUID bit
doesn't cover either of these models.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/cpu/mcheck/mce_intel.c diff | blob | history
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